The present circuit arrangement is directed to providing scrolling including both vertical scrolling and horizontal scrolling. As mentioned above we are discussing scrolling of a region and not an entire screen movement of visual data. In the prior art, scrolling has been accomplished by refreshing the scroll region together with other regions from the memory through a random access procedure and directing the information read from the memory to the screen. In this prior art arrangement sequential addressing of the memory is disrupted and because of such disruption such a system lacks flexibility in respect to defining the boundaries of scrolling. In some other arrangements data is copied from the memory through a device such as a DMA (Direct Memory Access) and returned to memory. A problem with such a system is that the rewrite consumes a relatively great amount of time (i.e., more than one vertical scan time), and the resulting scrolling procedure is normally not considered smooth. The present system operates at high speed and employs a technique which enables the bit map memory to be completely rewritten within one vertical scan. The system operates to display one pattern during a vertical scan while the memory is actually being reconfigured to another pattern. The memory is ready at the end of a vertical scan to be sequentially scanned a second time to display a different pattern and all of the changes required to display that different pattern have been made in the memory per se and not in some temporary storage device. The ability of the present system to reconfigure the memory within one vertical scan time is advantageous with respect to refreshing the memory. The techniques and hardware to refresh a bit map memory are well understood. In a system that addresses a bit map memory sequentially for screen refresh, the bit map memory is automatically refreshed one row at a time through registers. However, in a system that employs a random access of the bit map memory, special hardware is employed to refresh the memory. The present system is able to continually sequentially address the memory and hence does not require special hardware to refresh.